1. Field of the Invention
The present invention relates generally to gate electrodes employed within advanced Field Effect Transistors (FETs). More particularly, the present invention relates to a method for forming polycide gate electrodes employed within advanced Field Effect Transistors (FETs).
2. Description of the Related Art
Integrated circuits are formed upon semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by insulator layers.
As integrated circuit technology has advanced, there has been a continuing trend towards increasing levels of integrated circuit integration, integrated circuit performance and integrated circuit function. Within advanced integrated circuits within which there are formed Field Effect Transistors (FETs), such increasing levels of integrated circuit integration, integrated circuit performance and integrated circuit function have typically been achieved by simultaneously decreasing within those Field Effect Transistors (FETs) both the thicknesses of gate dielectric layers and the widths of semiconductor channel regions which are formed beneath those gate dielectric layers. The decreasing width of semiconductor channel regions within Field Effect Transistors (FETs) has in turn typically required a correlating decrease in areal dimensions of polysilicon gate electrodes which are conventionally employed as a masking element in defining within advanced Field Effect Transistors (FETs) the dimensions of semiconductor channel regions as well as the locations of source/drain regions which are separated by those semiconductor channel regions.
While the continuing increases in integration have successfully provided advanced generations of integrated circuits with increasing levels of performance and function, the continuing decreases in areal dimensions of polysilicon gate electrodes conventionally employed in forming Field Effect Transistors (FETs) within those advanced integrated circuits have required the use of polysilicon gate electrodes having low contact resistance layers formed upon their surfaces. The low contact resistance layers formed upon the polysilicon gate electrodes within advanced Field Effect Transistors (FETs) have typically been required in order to avoid contact resistance induced gate electrode electrical circuit delay which would otherwise result from higher contact resistance connections made directly to polysilicon gate electrodes of reduced areal dimension. The resulting polycide (polysilicon/metal silicide stack) gate electrodes have typically conventionally been formed as either a tungsten silicide polycide gate electrode or a titanium silicide polycide gate electrode, often through a self-aligned silicide (salicide) method which simultaneously provides corresponding tungsten silicide layers or titanium silicide layers upon the surfaces of adjoining source/drain regions of the Field Effect Transistor (FET) within which is formed the tungsten silicide polycide gate electrode or the titanium silicide polycide gate electrode. See, for example, Ahmad et al., U.S. Pat. No. 5,382,533, which illustrates the use of a tungsten silicide polycide gate electrode within a Field Effect Transistor (FET).
As areal dimensions of tungsten silicide polycide gate electrodes or titanium silicide polycide gate electrodes employed within Field Effect Transistors (FETs) have continued to decrease and define semiconductor channel regions beneath those tungsten silicide polycide gate electrodes or titanium silicide polycide gate electrodes of linewidth less than about 0.25 microns, the problem of contact resistance induced gate electrode electrical circuit delay again becomes important since the sheet resistances of both tungsten silicide layers and titanium silicide layers which define the contact resistances of both tungsten silicide polycide gate electrodes and titanium silicide polycide gate electrodes inherently increase dramatically at linewidths of less than about 0.25 microns. Thus, in order to avoid contact resistance induced gate electrode electrical circuit delay within integrated circuits having formed therein advanced Field Effect Transistors (FETs) with tungsten silicide polycide gate electrodes or titanium silicide polycide gate electrodes of linewidth less than about 0.25 microns, there has recently been proposed and implemented the use of polycide gate electrodes comprising cobalt silicide layers or nickel silicide layers rather than tungsten silicide layers or titanium silicide layers, since cobalt silicide and nickel silicide have an inherently lower contact resistance in comparison with either tungsten silicide or titanium silicide when formed in patterned layers of linewidth less than about 0.25 microns.
While the cobalt silicide polycide gate electrodes and nickel silicide polycide gate electrodes so formed have served well in providing gate electrodes exhibiting the decreased levels of contact resistance induced gate electrode electrical circuit delay desired within advanced integrated circuits, the methods through which such cobalt silicide polycide gate electrodes and nickel silicide polycide gate electrodes are formed within advanced Field Effect Transistors (FETs) are not entirely without problems. In particular, it is known in the art that the conventional self-aligned method for metal silicide layer formation within polycide gate electrodes, when employed for forming a cobalt silicide polycide gate electrode or nickel silicide polycide gate electrode, will typically yield a cobalt silicide layer or nickel silicide layer exhibiting substantial encroachment onto insulator spacers which adjoin the cobalt silicide polycide gate electrode or nickel silicide polycide gate electrode. Such encroachment may lead to electrical shorts between the cobalt silicide polycide gate electrode or the nickel silicide polycide gate electrode and the adjoining source/drain electrode regions which are separated by the insulator spacers, particularly under circumstances where the adjoining source/drain electrode regions also have simultaneously formed upon their surfaces self-aligned cobalt silicide layers or nickel silicide layers. It is thus in general towards the goal of forming within advanced Field Effect Transistors (FETs) cobalt silicide polycide gate electrodes, nickel silicide polycide gate electrodes and other metal silicide polycide gate electrodes which exhibit limited susceptibility to encroachment upon adjoining insulator spacers or source/drain regions that the present invention is directed.
Methods and materials through which may be formed within integrated circuits cobalt silicide layers and/or nickel silicide layers exhibiting desirable properties are known in the art. For example, Duchateau et al. in U.S. Pat. No. 5,302,552 disclose a method for forming without encroachment a self-aligned cobalt silicide layer or nickel silicide layer within an integrated circuit. The method employs annealing upon the exposed silicon portions of a silicon semiconductor substrate an amorphous alloy comprising cobalt or nickel in combination with an additional metal selected from the group of metals consisting of titanium, zirconium, tantalum, molybdenum, niobium and hafnium. In addition, Geiss et al. in U.S. Pat. No. 5,356,837 disclose a method for forming within a silicon semiconductor device an epitaxial cobalt silicide layer with limited susceptibility to agglomeration. The method employs annealing a silicon semiconductor device having formed thereover a bilayer comprising a cobalt layer formed over a refractory metal layer or a refractory metal silicide layer. Finally, Chen et al. in U.S. Pat. No. 5,457,069 disclose a method for forming within an integrated circuit a silicon semiconductor device having simultaneously formed thereover a titanium-tungsten barrier layer and a cobalt silicide layer or platinum silicide layer contacted shallow junction. The method employs forming and annealing upon the silicon semiconductor device a metal bilayer consisting of a lower metal layer comprising titanium metal alloyed with either cobalt metal or platinum metal, and an upper metal layer formed from tungsten.
Desirable in the art are additional methods and materials through which metal silicide layers such as cobalt silicide layers and nickel silicide layers may be formed within integrated circuits while exhibiting specific properties. Particular desirable are methods through which low resistance and high encroaching metal silicide layers such as cobalt silicide layers and nickel silicide layers when employed in forming polycide gate electrodes such as cobalt silicide polycide gate electrodes and nickel silicide polycide gate electrodes within Field Effect Transistors (FETs) within integrated circuits may be formed without encroachment of the low resistance and high encroaching metal silicide layers onto insulator spacers or source/drain regions adjoining the polycide gate electrodes formed with the low resistance and high encroaching metal silicide layers.